Dr Rinne Karl

Project Supervisor: Dr Karl Rinne Project No: KR1
Project Title: Verilog HDL Design and FPGA Implementation of a High Resolution Video Processor with Sprite Extension.
Course Suitability: LM118 BE in Electronic and Computer Engineering

Project Description:

An existing text-based VGA Video Processor (designed in Verilog-HDL and implemented on Xilinx FPGA supporting screen resolutions of 800x600 pixels with a 50MHz pixel clock) needs to be extended so that graphical sprites (small graphical objects) can be supported, placed and moved around the screen. The extensions allows for a minimum of eight independent 64x64 pixel colour sprites. Sprites can superimpose arbitrarily, with overlaps being detected and flagged. The video processor will be implemented in the Verilog HDL, targeting a Digilent FPGA prototyping platform (Nexys4) based on the high-performance Xilinx Artix-7 FPGA. The Nexys4 board incorporates all required hardware (video DAC, video port), no additional hardware is required. This project will appeal to students with a strong interest in advanced digital design, Verilog HDL, system architecture, on-chip bus architectures and video processing.

 

Project Supervisor: Dr Karl Rinne Project No: KR2
Project Title: Verilog HDL Design and FPGA Implementation of a Video Game (PONG)
Course Suitability: LM118 BE in Electronic and Computer Engineering

Project Description:

A legacy video game (PONG) with all its building blocks (VGA video processor, game control engine, user interface) should be designed in Verilog HDL, simulated/tested, documented and implemented on a Digilent Nexys4 FPGA prototyping platform based on the high-performance Xilinx Artix-7 FPGA. The game must support score counting, and gaming modes human-vs-machine, human-vs-human as well as machine-vs-machine (for demo purposes). The video game screen should be UL-branded (showing the UL crest in the centre of game play area). The target for screen resolution should be 800x600 pixels using a 50MHz pixel clock at 60Hz refresh rate.The Nexys4 board incorporates all required hardware (video DAC, video port), no additional hardware is required. This project will appeal to students with a strong interest in advanced digital design, Verilog HDL, systems-on-chip, and video processing.

 

Project Supervisor: Dr Karl Rinne Project No: KR3
Project Keywords: Analogue/mixed-signal IC design using the Cadence full-custom IC design tool chain (Cadence Virtuoso, Spectre).
Course Suitability: LM118 BE in Electronic and Computer Engineering

Project Description:

Project scope and details to be discussed at start of project.

 

Project Supervisor: Dr Karl Rinne Project No: KR4
Project Title: Python-Based Frequency Response Analysis and Measurement System for Server Power Supplies.
Course Suitability: LM118 BE in Electronic and Computer Engineering

Project Description:

This project focuses on the implementation of a Python-based frequency-response measurement system. The system will be used to characterise switching converters employed in compute servers. Centre-piece of the measurement system is an industry-standard frequency response analyser (N4L, PSM1735) connected via GPIB to a PC running a Linux OS (Ubuntu 16.04 LTS, or RHEL 6.8). The system will be able to measure converter frequency response of control, and determine key performance parameters (such as gain and phase margins). The software interfacing with the measurement equipment must be implemented in Python, and offer a simple user command line interface plus an optional GUI (TkInter). The measurement data will be processed and presented to the user using Python's NumPy and SciPy libraries. The software will facilitate data export to Scilab (or Matlab) and spreadsheets (Libreoffice) for post-processing. This project will appeal to students with a strong interest in Python programming, Linux OS, control systems, automated test equipment and instrumentation.